The present invention relates to on-chip impedance matching circuits, and more particularly, to on-chip impedance matching circuits that are sensitive to process, voltage, and temperature variations.
Prior art circuits have provided off-chip impedance matching circuits that reduce the e; reflection of signals on transmission lines. Off-chip impedance matching circuits typically include one or more off-chip resistors. The off-chip resistors are coupled to an input/output (I/O) pin of an integrated circuit to provide impedance matching.
Some integrated circuit have hundreds of I/O pins that require impedance matching circuitry. In these integrated circuits, a separate impedance matching resistor must be coupled to each of the I/O pins. Hundreds of impedance matching resistors must be coupled to such an integrated circuit to provide adequate impedance matching. Thus, prior art off-chip impedance matching circuits substantially increase the amount of board space required.
The present invention provides integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit. On-chip impedance matching circuits of the present invention are associated with a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and/or voltage are minimized.